CPU Features :
16-bit Data Bus
16-bit Address Bus
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| Figure 1.0 The architecture of CPU12 and its memory organisation |
**************** Following part is not included in CPU12 syllabus*************************
**************** Following part is not included in CPU12 syllabus*************************
This is computer architecture subject.
2-way set-associative cache memory
Firstly, you can choose how many way of set-associative mapping for instance, 2-way set-associative cache. If you have 16KB cache, it means that you have double size of main memory that is 32KB. If you select the 16-bit data bus width, it is equal to 2-byte lines of cache and if your cache memory is memory byte-addressable, thus you’ll get w=1 bit byte offset in line (2W=2 byte lines of cache). Then, you’ll get 13-bit (L) set index in cache. If the memory address size is 32-bit, then you’ll get the 18-bit (Tag) line tag. Refer to the calculation and illustration below so that you can more understand.
32KB main memory = 215 x 8 bits = 2n x 16 bits
2n = (215 x 8) / 16 = 16 384 = 214
16KB cache = 214 x 8 bits = 2L x 16 bits
2L = (214 x 8 bits) / 16 bits = 8192 = 213
i am doing the design of 16kb cache implementation fully associative.
ReplyDeletecan u help me how much to take the main memory size and division of tag bits and the data bits in cache memory.
I think your question is quite general. I've just realized your question when I opened back this subtopic in the class a week ago.
ReplyDelete